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9780071445641

Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification

Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification
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  • ISBN-13: 9780071445641
  • ISBN: 0071445641
  • Edition: 2
  • Publication Date: 2005
  • Publisher: McGraw-Hill Professional

AUTHOR

Zainalabedin Navabi

SUMMARY

LEARN VERILOG DESIGN WITH A MASTERThis rigorous tutorial shows electronics designers and students how to apply Verilog in sophisticated digital systems design, using over a hundred skill-building, fully worked-out, and simulated examples. Completely updated, the second edition covers Verilog 2001, new synthesis standards, testing and testbench developments, and the new OVL verification library. You'll find out just what's involved in using Verilog hardware description language (HDL) in digital system design. HDL expert Zain Navabi explains the design process in logical sequence -- the way it's done in the real world.Moving from simple concepts to the more complex, Navabi interprets Verilog constructs related to design stages and design abstractions, including behavioral description, dataflow description, and structure description. With emphasis on the concepts of concurrency and delay in hardware, the text helps you grasp the essence of HDLs. Clear specification of learning objectives at the beginning of each chapter and end-of-chapter problems focus attention on key concepts.If mastery of design with Verilog is the goal, Zain Navabi'sVerilog Digital System Designis the tool.MUST-HAVE CD INCLUDED: Verilog and VHDL simulators Synthesis tools Mixed-level logic and Verilog design environment FPGA design tools and environments from Altera Related tutorials and standards All worked examples from the book, including testbench and simulation-run reports for every example Complete CPU examples with Verilog code and software tools OVL verification libraries and tutorialsTHE BEST VERILOG TUTORIAL -- UPDATED: Verilog 2001, step by step in examples and text OVL verification library New synthesis standards New chapter on testbench development and verification Problem set in each chapter encourages review and test of key concepts Instructor's manual and lecture slides available for class useZainalabedin Navabi is the author of 'Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification', published 2005 under ISBN 9780071445641 and ISBN 0071445641.

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