Design and Development of a Configurable Fault-Tolerant Processor (CFTP) for Space Applications

The harsh radiation environment of space, the propensity for SEUs to perturb the operations of a silicon based electronics, the rapid development of microprocessor capabilities and hence software applications, and the high cost (dollars and time) to develop and prove a system, require flexible, reliable, low-cost, rapidly-developed system solutions. Consequently, a reconfigurable Triple Modular Redundant (TMR) System-on-a-Chip (SOC) utilizing Field Programmable Gate Arrays (FPGAs) provides a viable solution for space based systems. The Configurable Fault Tolerant Processor (CFTP) is such a system, designed specifically for the purpose of testing and evaluating, on orbit, the reliability of instantiated TMR soft-core microprocessors, as well as the ability to reconfigure the system to support any on board processor function. The CFTP maximizes the use of Commercial Off-The-Shelf (COTS) technology to investigate a low-cost, flexible alternative to processor hardware architecture, with a Total Ionizing Dose (TID) tolerant FPGA as the basis for a SOC. The flexibility of a configurable processor, based on FPGA technology, will en- able on-orbit upgrades, reconfigurations, and modifications to the architecture in order to support dynamic mission requirements. The CFTP payload consists of a Printed Circuit Board (PCB) of 5.3 inches x 7.3 inches utilizing a slightly modified PC/104 bus interface. The initial FPGA configuration will be an instantiation of a TMR processor, with included Error Detection and Correction (EDAC) and memory controller circuitry. The PCB is designed with requisite supporting circuitry including a configuration controller FPGA, SDRAM, and Flash memory in order to allow the greatest variety of possible configurations. The CFTP is currently manifested as a Space Test Program (STP) experimental payload on the Naval Postgraduate School's NPSAT1 and the United States Naval Academy's MidSTAR-1 satellites.Naval Postgraduate School Monterey CA is the author of 'Design and Development of a Configurable Fault-Tolerant Processor (CFTP) for Space Applications', published 2003 under ISBN 9781423501343 and ISBN 1423501349.